(a) Technical Field
The present disclosure relates generally to a method for manufacturing a semiconductor device and, more particularly, to manufacturing a semiconductor device in which an accumulation layer is formed on a side wall of a trench by accurately injecting ions in a silicon carbide MOSFET to which a trench gate is applied.
(b) Description of the Related Art
Recently, semiconductor devices have been designed to enable power having high breakdown voltage, high current, and high switching characteristics in order to satisfy larger application apparatuses. In such semiconductor devices, while very large current flows, low on-resistance or low saturation voltage is required in order to decrease power loss in a conducting state. Further, resistance to inverse high voltage of an PN junction, which is applied to both ends of the power semiconductor device in an off state or at the moment when a switch is off, i.e., high-breakdown voltage, is required.
A metal oxide semiconductor field effect transistor (MOSFET) in a semiconductor device is the most general field effect transistor in a digital circuit and an analog circuit. Meanwhile, in order to reduce the on-resistance and increase the current density, a trench gate MOSFET formed by removing a junction field effect transistor (JFET) area of a planar gate MOSFET has been researched.
In a trench gate MOSFET, after a trench is formed, ions are injected into the side wall of the trench to form an accumulation layer. In this case, a gate unit and a source unit need to be separated from each other, and at this time, an alignment error is generated. Thus, there is a problem in that the ions are not accurately injected.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the disclosure, and therefore, it may contain information that does not form the related art that is already known in this country to a person of ordinary skill in the art.